Architecture of a fieldbus message scheduler coprocessor based on the planning paradigm

The use of a centralised planning scheduler in fieldbus-based systems requiring real-time operation has proved to be a good compromise between operational flexibility and timeliness guarantees. It is particularly well adapted to embedded systems based on low-processing power microcontrollers due to the low overhead it imposes. In this paper a preliminary implementation of a hardware scheduling coprocessor based in the planning paradigm is presented. The coprocessor is installed in a special node of the fieldbus, the bus arbiter, and generates scheduling tables to be dispatched by the node CPU. With this solution it is possible to decrease the response time to changes in the system configuration or message parameters of the software-based planning scheduler. This opens the possibility of allowing automatic on-line changes requested by system nodes in addition to the ones requested by human operators, thus improving system reactivity. The paper includes a short review of the planning technique and a discussion on the motivation to develop the coprocessor as well as on recent similar and related work. The coprocessor architecture and several implementation details such as its interface with the arbiter CPU are presented. The initial calculations showing the feasibility of the unit are also derived, together with the first real implementation of the coprocessor itself.